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FPGA Design Engineer, India

We are looking for an individual who:

  • Works hard to meet deadlines
  • Pays close attention to details
  • Takes pride in his/her work but also welcomes criticism
  • Thrives in an environment of constant interaction, feedback and guidance
  • Asks lots of questions

Must Have:

  • Excellent revision control habits and experience with both distributed (e.g. Git) and centralized (e.g. SVN) revision control systems
  • 2+ years of experience in FPGA design
  • A solid understanding of Static Timing Analysis and Timing Closure techniques
  • An ability to learn new languages, methodologies and technologies

Good to Have:

  • University level knowledge of C and C++, preferably with 1+ year experience
  • Knowledge of clock domain crossing
  • Experience working in Linux
  • An understanding of standard protocols (e.g. PCIe, Ethernet, SDI, AXI, DDR SDRAM, etc.)

Location: India

Those with less than 5 years experience, please submit an
unofficial copy of your transcripts with your resume.

Evertz makes certain there is an equal employment opportunity for all employees and applicants for employment, including persons with disabilities. In compliance with AODA, Evertz will strive to provide accommodation to persons with disabilities in the recruitment process upon request. If you are selected for an interview and you require accommodation due to a disability during the recruitment process, please notify Human Resources upon scheduling your interview.

Thank you for considering a career with Evertz!

Apply Now!